Use of floating point multiply-accumulate (FMAC) operations are known in the art. An FMAC operation involves performing on three operands, A, B, and C, the operation A*B+C. FMAC operations are useful in that they may be used to implement both multiplication and division. For multiplication, the value of operand C is set to zero. For addition, the value of operand A is set to one. FMAC operations typically comply with an industry standard for use of floating point numbers, which are expressed in terms of both a mantissa and an exponent and are further explained in IEEE Standard for Binary Floating-Point Arithmetic, IEEE Std. 754-1985, incorporated herein by reference.
FMAC operations are implemented in multiple stages, and the final stage is used to normalize the value of the mantissa of the result. In particular, according to use of floating point numbers complying with the IEEE standard, the result is shifted to obtain a leading one in the mantissa and thus remove all leading zeros. This produces a normalized result for the FMAC operation. To obtain a leading one in the result, multiplexers are typically used in order to shift the result until the value one resides in the most significant bit position.
Multiplexers are known in the art and use control signals in order to shift input data among output lines based upon the control signals. Multiplexers can require many inputs for the data lines and the control signals, and each data input can require a separate data line and individual transistor for interfacing the data line with a corresponding logic gate that performs the data shifting. Due to the high number of inputs, individual data lines increase the number of transistors required for each gate, thus increasing the area and power consumption of each gate.
Accordingly, a need exists for a multiplexer for data shifting having reduced area and potentially other advantages.